Invalid register operand when updating
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. This is achieved, in part, by using a general purpose register to specify at least one memory address from which at least more than one, but typically several data path widths of data can be read.The present invention provides operands which are... To permit such a wide operand to be performed in a single cycle, a data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction. For example, a fetch stage may fetch instructions from main memory while an execution stage executes one or more previously fetched instructions. Typically, the pipeline stages process different portions of a stream of instructions concurrently.
FIELD OF THE INVENTIONThe present invention relates to a register renaming system that can process a large number of instructions per clock cycle in a processor based on superscalar architecture capable of out-of-order execution.Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. 08/328,185 has been abandoned in favor of continuation application Ser. During the dispatch of instructions from the instruction fetch buffer dispatch window, the destination result field of the instruction is renamed, and the most recent copy of the source operands are either tagged or supplied along with any instruction control bits to the reservation station entry identified by the rename tag.Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-of-order. for Apparatus to Dynamically Control the Out-of-Order Execution of Load/Store Instructions in a Processor Capable of Issuing and Executing Multiple Instructions in a Single Processor Cycle and assigned to a common assignee. The execution units 14, 20, 21, 22 and 23 are directed by the rename unit 12 to perform the oldest instruction that has each of its operands valid from one of the four reservation read ports P1A, P1B, P1C, or P1D.The technique utilizing a reorder buffer is adopted, for example, for the Pentium[tm] processor, available from Intel Corporation of Santa Clara, Calif. The technique utilizing a mapping table is described in Keller, R. The present invention has been proposed with a view to solving the foregoing problem.Its object is to provide a register renaming system whereby the number of instructions that can be processed per cycle could be increased beyond the current level.